In general, an image sensor is a semiconductor device that converts an optical image into electrical signals. The image sensor may be a Charge Coupled Device (CCD) image sensor, in which individual Metal Oxide Silicon (MOS) capacitors are located closely to each other such that charge carriers are stored in or discharged from the capacitors. A Complementary Metal Oxide Silicon (CMOS) image sensor employs a switching mode to sequentially detect output by providing MOS transistors corresponding to the number of pixels. CMOS technology may integrate peripheral devices, such as a control circuit and a signal processing circuit, into the sensor. The CMOS image sensor may include a photodiode and a MOS transistor in each unit pixel to detect signals in a switching mode and form images.
According to the related art, in a process of manufacturing the CMOS image sensor as described above, an NPN device can be manufactured by applying a CMOS process to an epitaxial layer. As shown in FIGS. 1 and 2, in the vertical NPN BJT device, a deep N-well layer 102 is formed over a substrate 100. A P-well 112 and an N-well 110 are formed over the deep N-well layer 102. An N type emitter E and a P type base B are formed in the P-well 112. An N type collector C is formed in the N-well 110. Shallow Trench Isolation (STI) areas 120 are formed among the emitter E, the base B and the collector C in order to isolate them from each other. An emitter contact area 126 and a collector contact area 130, into which high density N type ions are implanted, and a base contact area 128, into which P type ions are implanted, are formed over the upper portions of the emitter area, the collector area and the base area, respectively.
The deep N-well layer 102 allows electrons to flow from the N type emitter E toward the N type collector C. In this way, vertical collector current IC is generated in a normal active mode. In a BJT device, a ratio of collector current IC to base current IB (i.e. IC/IB) is referred to as a common emitter current gain (beta) and is an important factor that determines the DC performance of the device. Since the thickness and width of a single base layer are fixed by the manufacturing process, the optimal current gain of the related vertical BJT device cannot be obtained through a related CMOS process.